The present invention relates to memory devices, and more particularly relates to differential sensing of memory cells.
Flash memory devices include a memory array of memory cells arranged in rows and columns. A reference column of reference memory cells generates reference voltages for comparing to data stored in columns of memory cells. A sense circuit includes a plurality of sense amplifiers, a plurality of reference sense amplifiers, and a plurality of comparators. One of the sense amplifiers is coupled to a corresponding bit line that is coupled to a column of memory cells. Each of the reference sense amplifiers is coupled to a reference bit line that is coupled to the reference column of reference memory cells. One of the comparators is coupled to a corresponding sense amplifier and a corresponding reference sense amplifier for generating a signal indicative of the content of the read memory cell. The output of the comparator is latched and buffered. Before reading the memory cell, the bit line and the reference bit line are precharged. Before the data can be read and latched, the precharge voltage on the bit line and the reference bit line must settle.
The present invention provides a sense amplifier circuit that comprises a sense amplifier, a reference sense circuit and a comparator. The sense amplifier provides a sense signal in response to a voltage level on a bit line. The reference sense circuit provides a reference sense signal in response to a voltage on a reference column line. The reference sense circuit provides variable loading on the reference column line in response to a delay signal. The comparator provides a signal indicative of the signal on the bit line in response to the sense signal and the reference sense signal.
In one aspect of the invention, the delay signal is applied in response to a detected address transition. The delay signal may have a pulse width sufficient to allow precharge signals applied to the bit line and the reference bit line to achieve a near steady state condition.
In another aspect of the present invention, a memory circuit comprises an array of memory cells arranged in rows and columns and including a column of reference cells, a plurality of bit lines, and a reference bit line. Each of the plurality of bit lines connects a corresponding column of memory cells. The reference bit line connects the column of reference cells. A decoder is coupled to the rows of memory cells for selecting a row of memory cells and a corresponding reference cell in response to an address signal. An address detection circuit provides an address detection signal and a delay signal in response to a change of the address signal. A precharge circuit is coupled to the address detection circuit and the memory array for precharging the plurality of bit lines and the reference bit line in response to the address detection signal. A sense amplifier circuit comprises a sense amplifier, a reference sense circuit and a comparator. The sense amplifier provides a sense signal in response to a voltage level on a bit line. The reference sense circuit provides a reference sense signal in response to a voltage on a reference column line. The reference sense circuit provides variable loading on the reference column line in response to a delay signal. The comparator provides a signal indicative of the signal on the bit line in response to the sense signal and the reference sense signal.